The present invention relates to a reference voltage generator, and more specifically, to a reference voltage generator of a semiconductor memory device capable of generating a reference voltage having a stable voltage level regardless of temperature variation.
Generally, reference voltage generating circuits, which are used for an analog to digital converter (ADC), a digital to analog converter (DAC), and a low voltage dynamic random access memory (DRAM) device, are used to obtain a reference voltage having a voltage level insensitive to a variation in a temperature or a power voltage level.
In the conventional art, in order to obtain an accurate reference voltage, a reference voltage generator using a silicon band gap is often used. In order to generate a reference voltage having a stable voltage level even when there is a change in temperature, a voltage having a negative coefficient with respect to the temperature variation and a voltage having a positive coefficient with respect to the temperature variation are generated and added so that the temperature change coefficient may be ‘0’.
A voltage difference between a base and an emitter of a transistor is used as the negative coefficient voltage, and a voltage difference between a base and an emitter of another transistor, which is proportional to an absolute temperature, is used as the positive coefficient voltage.
FIG. 1 illustrates a circuit diagram of a conventional reference voltage generator.
Referring to FIG. 1, the conventional reference voltage generator includes a current generating unit 10, a reference voltage output unit 20 and a level shifter 30.
The current generating unit 10 generates a supply current It. The reference voltage output unit 20 outputs a first reference voltage Vout corresponding to the supply current It. The level shifter 30 shifts a voltage level of the first reference voltage Vout to output a second reference voltage Vout2.
The current generating unit 10 includes a current mirror unit 11, a temperature sensing unit 12, and a current supply unit 13.
The current mirror unit 11 supplies a mirrored current. As temperature increases, the temperature sensing unit 12 increases a current value of the mirrored current outputted from the current mirror unit 11. The current supply unit 13 generates the supply current It, which is in synchronization with a variation of the current value of the mirrored current output from the current mirror unit 11.
The current mirror unit 11 includes a plurality of MOS transistors MP0˜MP3, MN0, MN1, and a resistor R3.
The MOS transistor MP0 is coupled between a power voltage supply terminal VDD and the MOS transistor MP1. The MOS transistor MP2, coupled between the power voltage supply terminal VDD and the MOS transistor MP3, has a gate coupled with a gate of the MOS transistor MP0.
The MOS transistor MP1 is coupled between the MOS transistor MP0 and the MOS transistor MN0. The MOS transistor MP3, coupled between the MOS transistor MP2 and a first end of the resistor R3, has a gate coupled with a gate of the MOS transistor MP1 and a second end of the resistor R3. The first end of the resistor R3 is further coupled with a common node of the gates of the MOS transistors MP0 and MP2.
The resistor R3, which generates a reference current, is coupled between the MOS transistors MP3 and MN1. As described above, the second end of the resistor R3 is coupled with a common node of the gates of the MOS transistors MP1 and MP3.
The MOS transistor MN0, coupled between the MOS transistor MP1 and a bipolar transistor PNP0, has a gate coupled with a drain thereof. The MOS transistor MN1, coupled between the resistor R3 and a resistor R2, has a gate coupled with a common node of the gate and drain of the MOS transistor MN0.
Meanwhile, the temperature sensing unit 12 includes the bipolar transistors PNP0, a bipolar transistor PNP1, and the resistor R2.
The bipolar transistor PNP0, coupled between the MOS transistor MN0 and a ground voltage supply terminal VSS, has a base coupled to the ground voltage supply terminal VSS. The bipolar transistor PNP1, coupled between the resistor R2 and the ground voltage supply terminal VSS, has a base coupled with the base of the bipolar transistor PNP0.
The current supply unit 13 includes MOS transistors MP4 and MP5.
The MOS transistor MP4 and the MOS transistor MP5 are coupled in series between the power voltage supply terminal VDD and a node for outputting the first reference voltage Vout. The MOS transistor MP4 has a gate coupled with the gate of the MOS transistor MP2. The MOS transistor MP5 has a gate coupled with the gate of the MOS transistor MP3.
The reference voltage output unit 20 includes a resistor R1 and a bipolar transistor PNP2 that are serially coupled to each other.
The resistor R1 receives the supply current It through a first end. The bipolar transistor PNP2 is coupled between a second end of the resistor R1 and the ground voltage supply terminal VSS, and a base of the bipolar transistor PNP2 is coupled to the base of the bipolar transistors PNP0 and PNP1.
Meanwhile, a Widler type or band gap reference (BGR) type scheme has been widely used in a conventional reference voltage generator used in memory chips.
Although such reference voltage generator has benefits with respect to variations in manufacturing processes and power voltage, reference voltage level is sensitive to and may change depending on temperature variation, so that a voltage level of a source power of a transistor or a voltage level of a voltage generated from the comparison with a reference voltage is not stable. As a result, margin shortage or errors in a core operation of a semiconductor memory device may occur.
Moreover, a bipolar junction transistor (BJT) is used in the conventional reference voltage generator. A BJT occupies a large physical space, and its continuous operation causes large current consumption.
An analog circuit used in an integrated circuit primarily uses a bias circuit to set an operational point of the circuit. Particularly, a current reference circuit, which is a current source, is required to determine an operational characteristic of direct current (DC) and alternating current (AC) operations. The widely used bias circuit is affected by the variations of temperature, power voltage level, and manufacturing process.
Thus, a new bias circuit, which is less affected by variations of temperature, power voltage, and manufacturing process, is necessary. However, a conventional circuit that has lower dependency on temperature variation and is included in the conventional reference voltage generator, is complicated, occupies a large area in the semiconductor chip, and consumes a lot of power.